1. Field of the Invention
This invention pertains to the field of designing digital circuitry using programmable logic devices. More particularly, this invention pertains to a method and apparatus for accurately assigning timing delays from a cell within a programmable logic device to primitives in the designer's abstract representation of their circuit so that the timing characteristics of the overall circuit and of each primitive can be simulated and analyzed.
2. Background of the Invention
A field programmable gate array ("FPGA") is a relatively new type of programmable logic device, first introduced by Xilinx, Inc. in 1985. An FPGA includes cells which can be programmed to perform a variety of logical functions and also includes programmable interconnects to connect the logical cells in a general way. The cells and interconnects are used to implement complex logical circuits. The use of FPGAs continues to grow at a rapid rate due to the relatively shorter design cycles, reduced costs through logic consolidation and the flexibility offered by their re-programmability.
The digital circuit designer typically follows the pattern shown in FIG. 1 to implement a design in an FPGA.
The designer begins with an abstract representation 30 of the circuit to be implemented in the FPGA. This representation may be in the form of a schematic or in a hardware descriptive language such as VHDL. The abstract representation is provided to a technology mapper 32 which converts the representation into cells for implementation in an FPGA. A place and route operation 34 is performed to give the cells a geographic location in the FPGA and to interconnect the cells. At this point the designer has a circuit 34 which could be implemented into an FPGA. Typically, the designer next performs a simulation 36 of the FPGA circuitry in a logical simulator. The logical simulator is used to understand the logical correctness of the circuit as well as its timing behavior. If the designer is satisfied after analysis 38 of the simulation, he may decide 40 to encode 42 the FPGA circuit design and layout into a PROM which can download the circuit into the FPGA for operation. If, however, the designer is not satisfied with the analysis of the simulation, the designer can redesign 44 portions of the FPGA circuit to obtain more optimal logical or timing characteristics. After this redesign, further simulation 36 and analysis 38 may take place. This process can be repeated continuously until optimal results are achieved or other constraints cause the design phase to be halted or the design to be implemented.
This design approach has obvious problems and difficulties. The primary problem is the amount of time and effort consumed in repeated redesign. Typically, designers may choose FPGAs to implement designs operating at data speeds up to 25-35 mHz. Even if the designer wishes to implement designs operating in this range, it may be necessary for the designer to go through meticulous design capture and manual redesign of certain portions of the FPGA circuitry in order to achieve proper operation at these high speeds. In other words, the FPGA circuit design provided by the technology mapper may have be to modified to operate properly at the desired speed.
Complicating matters further, the technology mapper modifies the abstract circuit input by the designer while maintaining the specified relationship between inputs and outputs of the circuit. Thus, the technology mapper is likely to create a different internal circuit design than contemplated by the designer in order to optimally implement the circuit in the FPGA device. In so modifying the internal circuit design, certain intermediate logic and signals familiar to the designer may be eliminated.
Further, FPGA vendors specify timing characteristics of their FPGA circuitry only in terms of the timing relationship between the external pins on the internal components or cells, such as Xilinx's configurable logic blocks (CLBs). Each CLB typically includes a significant amount of digital circuitry. No internal timing information is given for this circuitry. Thus, the internal components of the CLB do not have timing characteristics specified for them. In addition, the designer is not presented with information relating the FPGA circuit to the abstract representation from which the FPGA circuit was created. For this reason, the designer cannot readily appreciate the timing limitations of the circuit in terms of his abstract representation.
Most importantly, logical simulations are run on the circuitry as laid out in the FPGA with the external timing characteristics. The designer, who typically visualizes the circuit in terms of the abstract representation rather than the FPGA circuit, has trouble working with, understanding and interpreting the logical simulation. It is against this background and to overcome the shortcomings of the prior art that the present invention has been developed.